Champion League (v220I, dual program, set 1)

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EMU Infos
dumper f205v
date 15/05/2010
emulator MAME 0.174
dev Roberto Fresca
PCB Infos
name chleagxa on ProgettoEMMA
chleagxa on Arcade Database
description Champion League (v220I, dual program, set 1)
year 1998
manufacturer Playmark

Contents

Technical references

CPUs

QTY Type clock position function
1x Z0840006PSC-Z80CPU u13 8-bit Microprocessor - main
1x CP82C55A u29 Programmable Peripheral Interface - main
1x PIC16C65A-20/P u1 8bit CMOS Microcontroller (internal ROM not dumped)
1x LM358 u4 Dual Operational Amplifier - sound
1x TDA2003 u6 Audio Amplifier - sound
1x YM2413 u3 FM Operator Type-M (OPM) - sound
1x oscillator 24.000000MHz x2
1x oscillator 3.579545 x1

ROMs

QTY Type position status
1x 27C020 u15 dumped
3x M27C1001 u9,u10,u11 dumped

RAMs

QTY Type position
2x U6264ADC u7,u14
2x HM3-65728BK-5 u22,u23

PLDs

QTY Type position status
2x A40MX04-PL84 u20,u21 not dumped
1x PALCE22V10H u16 not dumped

Others

1x 28x2 edge connector
1x 6 legs connector (J3)
1x pushbutton (S5 RESET)
1x trimmer (volume)
4x 8x2 switches DIP(DSW1-4)
1x 4x2 switches DIP (SW5)
1x battery 3.6V (BT1)

Notes

update 2016-04-17: u1 has been confirmed to be a PIC16C6x


update 2016-05-18 from Roberto Fresca:

This set has two different programs splitted in quarters.
Both programs are intended to cover playing cards graphics (2nd quarter program), or cans (lattine) graphics to avoid some italian laws... (4th quarter program).
Seems that there's no way to switch between them. They are harcoded through the involved PLD's. Addressing lines lower than A12 are driven normally.

Main program ROM banking through PLDs...

                                            27C2001
                                         .-----v-----.
                                   (VPP)-|01       32|-(VCC)
PALCE22V10H (u16) pin 21 (IO7) <---(A16)-|02       31|-(/P)
PALCE22V10H (u16) pin 05 (I4) <----(A15)-|03       30|-(A17)---> A40MX04-PL84 (u20) pin 37 (I/O)
PALCE22V10H (u16) pin 02 (I1) <----(A12)-|04       29|-(A14)---> PALCE22V10H (u16) pin 04 (I3)
RAM U6264ADC (u14) pin 03 (A7) <----(A7)-|05       28|-(A13)---> PALCE22V10H (u16) pin 03 (I2)
RAM U6264ADC (u14) pin 04 (A6) <----(A6)-|06       27|-(A8)----> RAM U6264ADC (u14) pin 25 (A8)
RAM U6264ADC (u14) pin 05 (A5) <----(A5)-|07       26|-(A9)----> RAM U6264ADC (u14) pin 24 (A9)
RAM U6264ADC (u14) pin 06 (A4) <----(A4)-|08       25|-(A11)---> RAM U6264ADC (u14) pin 23 (A11)
RAM U6264ADC (u14) pin 07 (A3) <----(A3)-|09       24|-(/G)
RAM U6264ADC (u14) pin 08 (A2) <----(A2)-|10       23|-(A10)---> RAM U6264ADC (u14) pin 21 (A10)
RAM U6264ADC (u14) pin 09 (A1) <----(A1)-|11       22|-(/E)
RAM U6264ADC (u14) pin 10 (A0) <----(A0)-|12       21|-(Q7)
                                    (Q0)-|13       20|-(Q6)
                                    (Q1)-|14       19|-(Q5)
                                    (Q2)-|15       18|-(Q4)
                                   (VSS)-|16       17|-(Q3)
                                         '-----------'

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