SRAM 1k x 8: Difference between revisions

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{| style="float: right;" border="1" cellpadding="4" cellspacing="0"
{| style="float: right;" border="1" cellpadding="4" cellspacing="0" class="sortable"
|+ style="background:silver" | Cross-Reference
|+ style="background:silver" | Cross-Reference
!BRAND
!BRAND
!TAG
!TAG
!NUMBER
!NUMBER
!PIN COUNT
!OUTPUT
!OUTPUT
!MARKINGS
!MARKINGS
|-
|-
|Cypress || CY7 || C130 || || CY7C130
|Cypress || CY || 7C130 || 48 || . || CY7C130 CY7C130A
|-
|-
|Intel || D/P || 2308 || TS || D2308
|Cypress || CY || 7C140 || 48 || . || CY7C140
|-
|-
|Mostek || MK || 4118 || || MK4118N MK4118J MK4118P
|Intel || D/P || 2308 || 24 || TS || D2308
|-
|Intel || D/P || 8185 || 18 || . || D8185
|-
|Mostek || MK || 4118 || 24 || . || MK4118N MK4118J MK4118P
|-
|Sony || CXK || 5808 || 22 || . || CXK5808
|}
|}


'''Static Random-Access Memory 1K x 8 (DIP24, 600mil)'''
'''Static Random-Access Memory 1K x 8 (DIP18, 300mil)(DIP22, 400mil)(DIP24, 600mil)(DIP48, 600mil)'''


=Size=
=Size=
Line 28: Line 35:
=Pinout=
=Pinout=
<pre>
<pre>
DIP48
          +---\/---+
    *CEl | 1    48| Vcc
    R/*Wl | 2    47| *CEr
  *BUSYl | 3    46| R/*Wr
    *INTl | 4    45| *BUSYr
    *OEl | 5    44| *INTr
      A0l | 6    43| *OEr
      A1l | 7    42| A0r
      A2l | 8    41| A1r
      A3l | 9    40| A2r
      A4l |10    39| A3r
      A5l |11    38| A4r
      A6l |12    37| A5r
      A7l |13    36| A6r
      A8l |14    35| A7r
      A9l |15    34| A8r
    I/O0l |16    33| A9r
    I/O1l |17    32| I/O7r
    I/O2l |18    31| I/O6r
    I/O3l |19    30| I/O5r
    I/O4l |20    29| I/O4r
    I/O5l |21    28| I/O3r
    I/O6l |22    27| I/O2r
    I/O7l |23    26| I/O1r
      GND |24    25| I/O0r
          +--------+
DIP24
DIP24
         +---\/---+
         +---\/---+
Line 42: Line 77:
     I/O2 |11    14| I/O4
     I/O2 |11    14| I/O4
     GND |12    13| I/O3
     GND |12    13| I/O3
        +--------+
DIP18
        +---\/---+
      A0 | 1    18| Vcc
      A1 | 2    17| RD
      A2 | 3    16| WR
      A3 | 4    15| ALE
      A4 | 5    14| CS
      A5 | 6    13| CE1
      A6 | 7    12| CE2
      A7 | 8    11| A9
    Vss | 9    10| A8
         +--------+
         +--------+
</pre>
</pre>


=External links=
=External links=
[http://en.wikipedia.org/wiki/Static_random-access_memory sRAM page on wikipedia]
[http://en.wikipedia.org/wiki/Static_random-access_memory SRAM page on wikipedia]


=Files=
=Files=
<gallery widths="150px">
<gallery widths="150px">
File:cy7c130.pdf|CY7C130 Datasheet
File:d2308.pdf|D2308 Datasheet
File:d2308.pdf|D2308 Datasheet
File:d8185.pdf|D8185 Datasheet
File:MK4118.pdf|MK4118 Datasheet
File:MK4118.pdf|MK4118 Datasheet
</gallery>
</gallery>


[[Category:RAM]]
[[Category:RAM]]
[[Category:DIP24]]
[[Category:DIP18-300mil]]
[[Category:DIP22-400mil]]
[[Category:DIP24-600mil]]
[[Category:DIP48-600mil]]

Latest revision as of 20:43, 26 May 2019

Cross-Reference
BRAND TAG NUMBER PIN COUNT OUTPUT MARKINGS
Cypress CY 7C130 48 . CY7C130 CY7C130A
Cypress CY 7C140 48 . CY7C140
Intel D/P 2308 24 TS D2308
Intel D/P 8185 18 . D8185
Mostek MK 4118 24 . MK4118N MK4118J MK4118P
Sony CXK 5808 22 . CXK5808

Static Random-Access Memory 1K x 8 (DIP18, 300mil)(DIP22, 400mil)(DIP24, 600mil)(DIP48, 600mil)

Size

bit Byte Hex
8Kb 1KB 2000hex

Pinout

DIP48
          +---\/---+
     *CEl | 1    48| Vcc
    R/*Wl | 2    47| *CEr
   *BUSYl | 3    46| R/*Wr
    *INTl | 4    45| *BUSYr
     *OEl | 5    44| *INTr
      A0l | 6    43| *OEr
      A1l | 7    42| A0r
      A2l | 8    41| A1r
      A3l | 9    40| A2r
      A4l |10    39| A3r
      A5l |11    38| A4r
      A6l |12    37| A5r
      A7l |13    36| A6r
      A8l |14    35| A7r
      A9l |15    34| A8r
    I/O0l |16    33| A9r
    I/O1l |17    32| I/O7r
    I/O2l |18    31| I/O6r
    I/O3l |19    30| I/O5r
    I/O4l |20    29| I/O4r
    I/O5l |21    28| I/O3r
    I/O6l |22    27| I/O2r
    I/O7l |23    26| I/O1r
      GND |24    25| I/O0r
          +--------+

DIP24
         +---\/---+
      A7 | 1    24| Vcc
      A6 | 2    23| A8
      A5 | 3    22| A9
      A4 | 4    21| *WE
      A3 | 5    20| *OE
      A2 | 6    19| *L
      A1 | 7    18| *CE
      A0 | 8    17| I/O7
    I/O0 | 9    16| I/O6
    I/O1 |10    15| I/O5
    I/O2 |11    14| I/O4
     GND |12    13| I/O3
         +--------+

DIP18
         +---\/---+
      A0 | 1    18| Vcc
      A1 | 2    17| RD
      A2 | 3    16| WR
      A3 | 4    15| ALE
      A4 | 5    14| CS
      A5 | 6    13| CE1
      A6 | 7    12| CE2
      A7 | 8    11| A9
     Vss | 9    10| A8
         +--------+

External links

SRAM page on wikipedia

Files

  • CY7C130 Datasheet
    CY7C130 Datasheet
  • D2308 Datasheet
    D2308 Datasheet
  • D8185 Datasheet
    D8185 Datasheet
  • MK4118 Datasheet
    MK4118 Datasheet
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