DRAM 256k x 8: Difference between revisions
From Citylan
Jump to navigationJump to search
m 1 revision |
mNo edit summary |
||
| Line 3: | Line 3: | ||
2Mb, 256KB, 40000hex8 bit | 2Mb, 256KB, 40000hex8 bit | ||
<pre> | |||
KM428C256 | |||
</pre> | |||
<pre> | <pre> | ||
+--\/--+ | +--\/--+ | ||
Revision as of 19:29, 23 September 2009
SRAM 256k x 8 (DIP32, 600mil)
2Mb, 256KB, 40000hex8 bit
KM428C256
+--\/--+
N.C.|1 32| Vcc
A16 |2 31| A15
A14 |3 30| CE2
A12 |4 29| WE/
A7 |5 28| A13
A6 |6 27| A9
A5 |7 26| A8
A4 |8 25| A11
A3 |9 24| OE/
A2 |10 23| A10
A1 |11 22| CS1/
A0 |12 21| IO7
IO0 |13 20| IO6
IO1 |14 19| IO5
IO2 |15 18| IO4
GND |16 17| IO3
+------+